FLOC 2018: FEDERATED LOGIC CONFERENCE 2018

This page contains an index consisting of author-provided keywords.

A
Automated digital control	Safe, Automated and Formal Synthesis of Digital Controllers for Continuous Plants
B
bounded synthesis	Maximum Realizability for Linear Temporal Logic Specifications
C
CounterExample Guided Inductive Synthesis	Safe, Automated and Formal Synthesis of Digital Controllers for Continuous Plants
D
decidability	On the Expressiveness of HyperLTL Synthesis
F
fixed-point algorithms for synthesis	Warm-Starting Fixed-Point Based Control Synthesis
H
hybrid systems	Safe, Automated and Formal Synthesis of Digital Controllers for Continuous Plants
hyperltl	On the Expressiveness of HyperLTL Synthesis
hyperproperties	On the Expressiveness of HyperLTL Synthesis
I
Invariant Checking	On Inductive Verification and Synthesis
Invariant Synthesis	On Inductive Verification and Synthesis
L
learning	Minimal Synthesis of String To String Functions From Examples
Linear Temporal Logic	Reactive Synthesis from LTL Specification with Spot Warm-Starting Fixed-Point Based Control Synthesis
Local Theory Extensions	On Inductive Verification and Synthesis
LTI systems	Safe, Automated and Formal Synthesis of Digital Controllers for Continuous Plants
M
maximum realizability	Maximum Realizability for Linear Temporal Logic Specifications
MaxSAT	Maximum Realizability for Linear Temporal Logic Specifications
mealy machine	Minimal Synthesis of String To String Functions From Examples
N
non-deterministic mealy machine	Minimal Synthesis of String To String Functions From Examples
O
omega-automata	Reactive Synthesis from LTL Specification with Spot
P
parity games	Reactive Synthesis from LTL Specification with Spot
Program Synthesis	Programming by example: efficient, but not “helpful”
Programming by example	Programming by example: efficient, but not “helpful”
Q
quantifier elimination	On Inductive Verification and Synthesis
R
reactive synthesis	Reactive Synthesis from LTL Specification with Spot Maximum Realizability for Linear Temporal Logic Specifications
S
SMT	On Inductive Verification and Synthesis
Symbol Elimination	On Inductive Verification and Synthesis
Symbolic execution	Scalable Synthesis with Symbolic Syntax Graphs
synthesis	Safe, Automated and Formal Synthesis of Digital Controllers for Continuous Plants Minimal Synthesis of String To String Functions From Examples Scalable Synthesis with Symbolic Syntax Graphs
T
temporal logic	Maximum Realizability for Linear Temporal Logic Specifications
type systems	Scalable Synthesis with Symbolic Syntax Graphs
U
User Studies	Programming by example: efficient, but not “helpful”
W
warm-start	Warm-Starting Fixed-Point Based Control Synthesis

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