FLOC 2018: FEDERATED LOGIC CONFERENCE 2018
Program Verification in the Presence of Cached Address Translation

Authors: Hira Syeda and Gerwin Klein

Paper Information

Title:Program Verification in the Presence of Cached Address Translation
Authors:Hira Syeda and Gerwin Klein
Proceedings:ITP Papers
Editors: Jeremy Avigad and Assia Mahboubi
Keywords:Translation Lookaside Buffer (TLB), Operating System Verification, Program Verification, Cached Address Translation, Security, Isabelle/HOL Theorem Proving
Abstract:

ABSTRACT. Operating system (OS) kernels achieve isolation between user-level processes using multi-level page tables and translation lookaside buffers (TLBs). Controlling the TLB correctly is a fundamental security property --- yet all large-scale formal OS verification projects leave the TLB as an assumption. We present a logic for reasoning about low-level programs in the presence of TLB address translation. We extract invariants and necessary conditions for correct TLB operation that mirror the informal reasoning of OS engineers. Our program logic reduces to a standard logic for user-level reasoning, reduces to side-condition checks for kernel-level reasoning, and can handle typical OS kernel tasks such as context switching and page table manipulations.

Pages:18
Talk:Jul 11 09:00 (Session 60D)
Paper: